Metallic Bump Structure Without Under Bump Metallurgy And a Manufacturing Method Thereof

ABSTRACT

The metallic bump is directly formed on a semiconductor wafer&#39;s I/O pad without UBM. First, a zinc layer is formed on the I/O pad or an anti-oxidation layer of the I/O pad is selectively etched off. Then, an isolative layer and a copper foil are arranged sequentially in this order above the I/O pad. The isolative layer is originally in a liquid state or in a temporarily solid state and later permanently solidified. Then, a via above the I/O pad is formed by removing part of the isolative layer and the cooper foil. Subsequently, A thin metallic layer connecting the copper foil and the I/O pad is formed in the via and a plating resist on the copper foil is formed. Then, a metallic bump is formed from the via whose height is controlled by the plating resist. Finally, the plating resist and the copper foil are removed.

CROSS-REFERENCES TO RELATED APPLICATIONS

This is a division of U.S. application Ser. No. 12/246,486, filed Oct.6, 2008, which is incorporated herewith in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to flip-chip packaging, and moreparticularly to a method of forming metallic bumps on the I/O pads of asemiconductor device without under bump metallurgy and a metallic bumpstructure thus formed.

2. The Prior Arts

Flip-chip packaging utilizes bumps to establish electrical contactbetween the I/O pads of a semiconductor die (e.g., a chip) and thesubstrate or lead frame of the package. Conventionally, there is aso-called under bump metallurgy (UBM) located between the bump and anI/O pad of the semiconductor die.

An UBM generally contains an adhesion layer, a barrier layer and awetting layer, arranged in this order on top of an I/O pad. The bumpsthemselves, based on the material used, could be classified as solderbumps, gold bumps, copper pillar bumps and bumps with mixed metals.

To form bumps on the UBMs, usually a technique such as electroplating,printing, or stud bonding is used. For electroplating, patterned platingresists are first formed on the UBMs and then metals are plated. Forprinting, solders are first printed on the UBMs and the solders arethermally cured into the bumps. For stud bonding, it is used for limitedgold bumping only. The semiconductor die with bumps is then singulatedfrom the semiconductor wafer, and soldered onto a substrate or leadframe.

UBM not only prevents the copper trace on the semiconductor die fromdissolution into solder but also functions as a conducting plate ifelectroplating is the means of forming metallic bump. Besides, thewetting layer of the UBM provides reliable solderability for formingsolder bump, if aluminum is used in the I/O pad.

SUMMARY OF THE INVENTION

Accordingly, a major objective of the present invention is to provide amethod of forming metallic bumps directly on a semiconductor wafer's I/Opads without the expensive UBM process. The I/O pads could be made ofcopper or aluminum and, if the I/O pads are made of copper, could havean anti-oxidation layer made of aluminum or other anti-oxidationmaterial.

According to an embodiment of the present invention, the method containsthe following major steps. First, a zinc layer is formed on a topsurface of the aluminum I/O pad or an anti-oxidation layer of the I/Opad is selectively etched off. Then, an isolative layer and a copperfoil are arranged sequentially in this order above the I/O pad. Theisolative layer is originally in a liquid state or in a temporarilycured state and later permanently solidified so as to reliably adhere tothe semiconductor die. Then, a via above the I/O pad is formed byremoving part of the isolative layer and the copper foil. Subsequently,a thin metallic layer connecting the copper foil and I/O pad isdeposited in the via and a plating resist on the copper foil islaminated. Then, by using the copper foil and the thin metallic layer toconduct electrical current, a metallic bump is plated from the via,whose height is controlled by the plating resist. Finally, the platingresist and the copper foil are removed.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become better understood from a careful readingof a detailed description provided herein below with appropriatereference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1H show the results of the steps of forming a metallic bumpon an I/O pad according to an embodiment of the present invention.

FIG. 2 is a schematic top view showing a semiconductor die of asemiconductor wafer having rerouted metallic bumps and plating net.

FIGS. 3A to 3D show the additional steps of extending the method ofFIGS. 1A to 1H to achieve bump rerouting.

FIGS. 4A to 4E show the steps to achieve bump rerouting through twolayers of traces.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The following descriptions are exemplary embodiments only, and are notintended to limit the scope, applicability or configuration of theinvention in any way. Rather, the following description provides aconvenient illustration for implementing exemplary embodiments of theinvention. Various changes to the described embodiments may be made inthe function and arrangement of the elements described without departingfrom the scope of the invention as set forth in the appended claims.

FIGS. 1A to 1H show the results of the steps of forming a metallic bumpon an I/O pad of a semiconductor wafer according to an embodiment of thepresent invention. As shown in FIG. 1A, the I/O pad 12 is located on aside of a semiconductor die 10 which can be an integrated circuit (IC),a transistor, a diode, or a thyristor, etc. For ease of reference, thisside is referred to as the active side of the semiconductor die 10.Please note that the semiconductor die 10 is actually part of and notyet singulated from a semiconductor wafer (not shown). The semiconductorwafer could have a number of dice 10 and each semiconductor die 10 couldhave a number of I/O pads 12. For ease of understanding, only onesemiconductor die 10 and one I/O pad 12 are shown in the accompanieddrawings. Also on the active side of the semiconductor die 10, there isa passivation layer 14 which exposes part of a top surface of the I/Opad 12. Please also note that the term “semiconductor device” is used inthe present specification could mean a semiconductor die as illustratedor a semiconductor wafer containing a number of these semiconductordice.

The I/O pad 12 could be made of aluminum or copper. If the I/O pad 12 ismade of copper, the I/O pad 12 usually has an anti-oxidation layer 16made of aluminum or other anti-oxidation material to entirely cover theexposed top surface of the I/O pad 12. If the I/O pad 12 is made ofaluminum, there is usually no anti-oxidation layer. If the I/O pad 12 ismade of aluminum or, if the I/O pad 12 is made of copper having analuminum anti-oxidation layer 16, a zinc layer is first coated on thealuminum surface of the I/O pad 12 by an immersion zinc process commonlyknown as zincation. In an alternative embodiment where the I/O pad 12 ismade of copper having an anti-oxidation layer 16 made of aluminum orother anti-oxidation material, instead of coating the zinc layer, theanti-oxidation layer 16 is removed first by selective etching to exposethe copper I/O pad 12 before performing the subsequent steps. The resultwould be similar to that of FIG. 1A without the anti-oxidation layer 16.

As a brief summary, there are three possible combinations: (1) a zinclayer coated on the aluminum I/O pad 12; (2) a zinc layer coated on thealuminum anti-oxidation layer 16 of the copper I/O pad 12; or (3) thecopper I/O pad 12 is exposed by selectively etching off theanti-oxidation layer 16 made of aluminum or other anti-oxidationmaterial. The zinc layer is usually very thin. Therefore, forsimplicity, in the following the combination (2) (i.e., there is ananti-oxidation layer 16 and a zinc layer is coated on the anti-oxidationlayer 16) is mainly used as example and the zinc layer is too thin to beshown. As to the combinations (1) and (3), the following descriptioncould be easily extended by imaging that the anti-oxidation layer 16 inthe accompanied drawings does not exist.

Then, an isolative layer 18 and a copper foil 20 are provided as shownin FIG. 1B. The isolative layer 18 and the copper foil 20 are arrangedsequentially in this order on a top surface of the structure of FIG. 1Aand the result is shown in FIG. 1C. The material for the isolative layer18 is one such that the isolative layer 18 is in a liquid state (AStage) or in a temporarily cured state (B Stage), so that the isolativelayer 18 can reliably adhere to the structure of FIG. 1A. Various typesof polymers such as epoxy resin are ideal materials for the isolativelayer 18. Then, by applying appropriate heat and pressure to theisolative layer 18 in the liquid state or in the temporarily curedstate, the isolative layer 18 is permanently solidified (C Stage) andthereby tightly adheres to the structure of FIG. 1A. If an isolativematerial in temporarily cured state is chosen, the isolative materialshould be able to turn into liquid state again within a specifictemperature range during curing. In one embodiment, the copper foil 20is coated with the isolative layer 18 first, and the combination is thenstacked to the top surface of the structure of FIG. 1A. Subsequently, byapplying appropriate heat and pressure to the isolative layer 18, it ispermanently solidified, thereby tightly adheres to the structure of FIG.1A. In an alternative embodiment, the isolative layer 18 is in atemporarily cured state or a liquid state and is stacked on the topsurface of the structure of FIG. 1A first. Subsequently, the copper foil20 is stacked on the top surface of the isolative layer 18. Then, byapplying appropriate heat and pressure, the isolative layer 18 ispermanently solidified, thereby tightly adheres to the structure of FIG.1A. Optionally, the isolative layer 18 can be reinforced with glassfiber. In addition, the copper foil 20 could be optionally thinned downif a fine pitch bump or tiny bump is to be formed.

Then, a part of the copper foil 20 above the I/O pad 12 is removed bylaser ablation or chemical etching first and then a part of theisolative layer 18 above the I/O pad 12 is removed by laser ablation orlithographic means. A via 22 exposing a top surface of the zinc layer ofthe I/O pad 12 (or, the copper I/O pad 12 if anti-oxidation layer 16 isetched off earlier by selective etching) is thereby formed as shown inFIG. 1D. During the lamination of the copper foil 20 and the isolativelayer 18 on the semiconductor device, the semiconductor device can be awhole semiconductor wafer without separation or part of a semiconductorwafer after cutting and separation.

As mentioned earlier, if the I/O pad 12 is made of aluminum or the I/Opad 12 has anti-oxidation layer 16 made of aluminum, the zinc layer iscoated on the I/O pad 12 or the aluminum anti-oxidation layer 16 of theI/O pad 12 by an immersion zinc process before the stacking of theisolative layer 18 and the copper foil 20. In an alternative embodiment,the zinc layer could be coated on the I/O pad 12 or the aluminumanti-oxidation layer 16 of the I/O pad 12 by an immersion zinc processafter the via 22 of FIG. 1D is formed with the same method mentionedabove. If the I/O pad 12 is made of copper having an anti-oxidationlayer made of aluminum or other anti-oxidation material, selectivelyetching the anti-oxidation layer off to expose the copper I/O pad 12 canalso be carried out after the via 22 of FIG. 1D is formed.

Subsequently, a thin metallic layer 24 is formed at least in the via 22by using electroless deposition of copper or nickel so that the thinmetallic layer 24 connects the copper foil 20 to the top surface of thezinc layer (or the copper I/O pad 12 if the anti-oxidation layer 16 isetched off selectively), as shown in FIG. 1E. For enhanced reliability,optionally, an additional metal layer could be further formed byelectroplating (or electroless deposition) on an external surface of thethin metallic layer 24. For simplicity, the plated metal layer is notshown. Then, a plating resist 26 is coated by using a photo imageablefilm lamination and patterned by applying light exposure selectively ona top surface of the copper foil 20 with a plating opening (notnumbered) to expose the via 22 coated with the thin metallic layer 24 asshown in FIG. 1F. As such, the copper foil 20 and the thin metalliclayer 24 together can jointly conduct electrical current to plate ametallic bump 28 in the via 22 above the I/O pad 12, as shown in FIG.1G. The material of the metallic bump 28 could be chosen from a group ofgold, copper, tin, nickel, solder, and a combination thereof, which hasgood adhesion capability to the thin metallic layer 24 and goodsolderability in assembly.

Finally, as shown in FIG. 1H, the plating resist 26 is stripped off and,by using laser or chemical etching, part of the copper foil 20 under theplating resist 26 is also removed. Then, the metallic bump 28 can befurther and optionally covered with a coating layer 30 at least on a topsurface of the metallic bump 28 (in the drawing, the metallic bump 28 isentirely covered) so as to prevent the metallic bump 28 from oxidationbefore assembly. Depending on the material of the metallic bump 28,various materials could be used as the coating layer 30. For example,for nickel bump 28, a coating layer 30 made of gold could be used and,for copper bump 28, the coating layer 30 could be made of OSP (OrganicSolderability Preservative), electroless nickel immersion gold,immersion silver or immersion tin, just to name a few. In an alternativeembodiment, the coating layer 30 is formed on a top surface of thestructure of FIG. 1G by electroplating before the plating resist 26 isstripped off. Then, the plating resist 26 and part of copper foil 20under the plating resist 26 are removed. The produced result would besimilar to that of FIG. 1H except that there is no coating layer 30 atthe lateral sides of the metallic bump 28. The formation of the metallicbump 28 is therefore completed. The height of the metallic bump 28 canbe controlled by having the plating resist 26 to be of an appropriateheight and the width of the metallic bump 28 is determined by adjustingthe aperture of the plating opening on the plating resist 26.

In an alternative embodiment, the isolative layer 18 in a liquid stateis applied to the structure of FIG. 1A alone without the copper foil 20.The isolative layer 18 is then solidified into the temporarily curedstate first and the via 22 exposing the zinc layer of the I/O pad 12 (orthe copper I/O pad 12 if the anti-oxidation layer 16 is etched offselectively) is formed. Then, the copper foil 20 is stacked on thetemporarily cured isolative layer 18. Afterwards, the isolative layer 18is solidified permanently together with the copper foil 20. Then, afterpart of the copper foil 20 above the via 22 is removed by chemicaletching or laser ablation, the result is the same as what is shown inFIG. 1D. The same subsequent steps as described above can be conductedto form the metallic bump 28. During the coating of the isolative layer18 on the semiconductor device, the semiconductor device can be a wholesemiconductor wafer without separation or part of a semiconductor waferafter cutting and separation.

In yet another alternative embodiment where the copper foil 20 is notused at all, the isolative layer 18, in a liquid state or a temporarilycured state, is stacked on the structure of FIG. 1A and solidifiedpermanently alone. Then, the via 22 exposing the zinc layer of the I/Opad 12 (or the copper I/O pad 12 if the anti-oxidation layer 16 isetched off selectively) is formed. The thin metallic layer 24 issubsequently formed on the top surface of the isolative layer 18 and inthe via 22 by sputtering or electroless deposition. The thin metalliclayer 24 is then optionally thickened to achieve better conductivity byelectroplating (or electroless deposition) and the result would besimilar to what is shown in FIG. 1E. The thickened metallic layer 24 ontop of the isolative layer 18 will perform the function of the copperfoil 20 in previous embodiments. The same subsequent steps as describedabove can be conducted to form the metallic bump 28. In this embodiment,an isolative layer such as ABF (Ajinomoto Build-up Film) with goodadhesion to electroless metallic deposition is preferable for betterreliability, particularly while rerouting is required in the bumpingprocess. During the coating of the isolative layer 18 on thesemiconductor device, the semiconductor device can be a wholesemiconductor wafer without separation or part of a semiconductor waferafter cutting and separation.

In still another alternative embodiment where the isolative layer 18 isalso stacked on the structure of FIG. 1A without the copper foil 20 andsolidified permanently alone, the thin metallic layer 24 is formed onthe top surface of the isolative layer 18 by sputtering or electrolessdeposition. The via 22 exposing the zinc layer of the I/O pad 12 (or thecopper I/O pad 12, if the anti-oxidation layer 16 is etched offselectively) is then formed. Subsequently, the thin metallic layer 24 isformed again to cover at least the via 22 by electroless deposition orsputtering. The thin metallic layer 24 is optionally thickened toachieve better conductivity by electroplating (or electrolessdeposition) and the result would be similar to what is shown in FIG. 1E.The thickened metallic layer 24 on top of the isolative layer 18 willperform the function of the copper foil 20 in previous embodiments. Thesame subsequent steps as described above can be conducted to form themetallic bump 28. During the coating of the isolative layer 18 on thesemiconductor device, the semiconductor device can be a wholesemiconductor wafer without separation or part of a semiconductor waferafter cutting and separation.

To form the via 22 so that it exposes the zinc layer of the I/O pad 12(or the copper I/O pad 12, if the anti-oxidation layer 16 is etched offselectively) precisely, the location coordinates of the I/O pad 12 hasto be determined first. To achieve that, fiducial marks can be preparedin advance on a bottom side of the semiconductor device. Then, byinspecting the coordinates of the fiducial marks and their positionalrelationship to the I/O pad 12, the exact location coordinates of theI/O pad 12 can be determined. An alternative approach is to utilize anX-ray apparatus that penetrates through the copper foil 20 of FIG. 1C todirectly determine the exact location coordinates of the I/O pad 12.Another alternative approach is, after removing part of the copper foil20, to use a camera to detect the fiducial marks on the semiconductordevice and then calculate the location coordinates of the I/O pad 12.

Bump rerouting is sometimes required because metallic bumps on originallocations of the I/O pads are not suitable for soldering in thefollowing assembly process and the conventional UBM process couldrearrange the bumps to appropriate locations for subsequent soldering.Since the present invention omits the expensive UBM process, to achievebump rerouting as shown in FIG. 2, the rerouted bumps 28A and therouting traces 42 laterally to the vias 22 have to be formed atappropriate locations. FIGS. 3A through 3D show the additional steps ofextending the method of the present invention to achieve bump rerouting.

FIG. 3A shows a structure which is formed according to the stepsillustrated by FIGS. 1A to 1F. The structure of FIG. 3A, however, isdifferent from that of FIG. 1F in that the plating resist 26 has aplating opening 40 to expose not only the via 22, but also a designatedlocation of the rerouted metallic bump 28A and a laterally routing trace42 connecting the designated location of the metallic bump 28A and thevia 22. To improve mechanic strength of the rerouted metallic bump 28A,ablating a blind hole 60 concurrently with the via 22 under thedesignated location of the rerouted metallic bump 28A is recommended.The thin metallic layer 24 is also deposited into the blind hole 60under the rerouted metallic bump 28A as well before the plating resist26 is laminated. Alternatively, a conductive paste can be filled intothe blind hole 60 and solidified to replace the deposition of thinmetallic layer 24.

Then, as shown in FIG. 3B, copper or other suitable metal is plateduntil a designed thickness is reached so as to form the routing trace42. Subsequently, as shown in FIG. 3C, a second plating resist 26A isformed on a top surface of the plating resist 26 and the routing trace42 with opening 40A only at the designed location of the reroutedmetallic bump 28A (i.e., above the blind hole 60), and an appropriatemetal such as copper, nickel, solder, tin, gold, or a combinationthereof is plated until the rerouted metallic bump 28A is formed at thedesigned location with a designed thickness. Finally, as shown in FIG.3D, the plating resists 26 and 26A are removed, and part of the copperfoil 20 under the plating resist 26 is etched off by chemical etching orlaser ablation so that the rerouted metallic bump 28A and the connectingtrace 42 are completed. Optionally, a solder mask will be subsequentlyapplied to cover the via 22 and routing trace 42 for protection.

In an alternative embodiment, the plating resist 26 has plating openingto expose the via 22, the designed location of rerouted metallic bump28A, the laterally routing trace 42 connecting via 22 and the designatedlocation, and one or more plating bars 52 connecting a plating net(i.e., a net containing the rerouted metallic bump 28A, the via 22, andthe routing trace 42) to an plating electrode 50 of the semiconductorwafer as shown in FIG. 2. Then, copper or other suitable metal is platedto a designed thickness to form the routing trace 42 and the plating bar52. The plating resist 26 is first stripped off and part of the copperfoil 20 under the plating resist 26 is etched off by laser ablation orchemical etching. Then, an optional solder mask is applied on thesemiconductor die 10 with opening on the designed location of reroutedmetallic bump 28A. Subsequently, a second plating resist 26A islaminated on the solder mask with opening on the designed location ofrerouted metallic bump 28A. An appropriate metal such as copper, nickel,solder, tin, gold, or a combination thereof is plated using the platingbar 52 to conduct electrical current until the rerouted metallic bump28A is formed at the designed location with a designed thickness.Finally, the second plating resist 26A is stripped off and the platingbar 52 is etched off. The rerouted metallic bump 28A is then completed.Please note that these steps are quite similar to the previousembodiments and therefore no additional drawing is provided.

Sometimes, if rerouting is difficult to achieve with a single layer oftrace as described above, multiple layers of traces could be used withthe routing trace(s) on the lower layer(s) ended at some intermediatepoint(s). One embodiment is described as follows and shown in FIGS. 4Ato 4D. According to the steps 1A to 1F and after the thin metallic layer24 is coated in the via 22, the plating resist 26 is laminated on thecopper foil 20 with opening to expose the via 22, an intermediatelocation, and the laterally routing trace 42 connecting the via 22 andthe intermediate location, as shown in FIG. 4A. Copper or other suitablemetal is plated until a designed thickness is achieved to form therouting trace 42, as shown in FIG. 4B. Then the plating resist 26 isstripped off and part of copper foil 20 under the plating resist 26 isetched off by laser ablation or chemical etching. Then, a secondisolative layer 68 and a second copper foil 70 are laminated on thesemiconductor die 10 and permanently solidified, as shown in FIG. 4C.Please note that the various approaches in laminating the secondisolative layer 68 and the second copper foil 70 described above couldbe applied here as well and their details are omitted here forsimplicity. A part of the second copper foil 70 and the second isolativelayer 68 on top of the intermediate location is removed by similarmethods mentioned above for form a second via 72 exposing theintermediate location, as shown in FIG. 4D. Again, to improve mechanicstrength of the rerouted metallic bump 28A, ablating a blind hole 74concurrently with the second via 72 under the designated location of thererouted metallic bump 28A is recommended. Then, a thin metallic layer76 is deposited into the blind hole 74 under the rerouted metallic bump28A and the second via 72. Alternatively, a conductive paste can beplugged into the blind hole 74 and solidified to replace the depositionof thin metallic layer 74.

The similarity between the structure shown in FIG. 4D and the structureshown in FIG. 3A should be quite straight forward. Therefore, the samesteps described in FIG. 3A to FIG. 3D are conducted to form a secondlayer of trace 78 and the rerouted metallic bump 28A connected to thesecond via 72 at the intermediate location by the second layer of trace78. The result is illustrated in FIG. 4E. The foregoing processes couldactually be repeated to reroute the metallic bump through moreintermediate locations and more layers of routing traces.

The most significant benefits of the present invention are as follows.First an element selected from a large collection of highly conductivemetallic materials such as gold, silver, palladium, copper, tin, solder,nickel, etc., or any combination of these highly conductive metallicmaterials can be used to form the metallic bump 28 through electrolessdeposition and electroplating. Secondly, the metallic bump 28's bondingto the semiconductor die 10 is enhanced by the additional adhesionprovided by the isolative layer 18, thereby achieving a superior bondingbetween the metallic bump 28 and the semiconductor die 10. Thirdly, theexpensive UBM process could be omitted entirely because, instead of UBM,the copper foil 20 functions as an electroplating connection during theformation of the metallic bumps and a chosen barrier layer coated onmetallic bump 28 can protect the copper trace from dissolving if copperis used in I/O pad, thereby lower down the production costsignificantly.

Although the present invention has been described with reference to thepreferred embodiments, it will be understood that the invention is notlimited to the details described thereof. Various substitutions andmodifications have been suggested in the foregoing description, andothers will occur to those of ordinary skill in the art. Therefore, allsuch substitutions and modifications are intended to be embraced withinthe scope of the invention as defined in the appended claims.

1. A metallic bump structure on an I/O pad on an active side of asemiconductor die, comprising: an isolative layer and a copper foil inthis order on said active side of said semiconductor die, said isolativelayer and said copper foil having a via above said I/O pad; a thinmetallic layer at least in said via, said thin metallic layer connectedto said copper foil and said I/O pad; and a metallic material filled insaid via and extended vertically above said copper foil and saidisolative layer for an appropriate thickness.
 2. The metallic bumpstructure according to claim 1, further comprising: if said I/O pad ismade of aluminum or said I/O pad has an anti-oxidation layer made ofaluminum, a zinc layer on a top surface of said aluminum I/O pad or saidaluminum anti-oxidation layer.
 3. The metallic bump structure accordingto claim 1, wherein said isolative layer is in one of a temporarilycured state and a liquid state before being applied to said active side.4. The metallic bump structure according to claim 1, wherein said thinmetallic layer is made of one of copper and nickel.
 5. The metallic bumpstructure according to claim 1, wherein said metallic material is one ofgold, copper, tin, nickel, solder, and a combination thereof.
 6. Themetallic bump structure according to claim 1, further comprising: acoating layer for anti-oxidation at least on a top surface of saidmetallic material.
 7. The metallic bump structure according to claim 1,wherein said metallic material laterally extends above said copper foiland said isolative layer from said via to one of a rerouted location andan intermediate location of a metallic bump.
 8. The metallic bumpstructure according to claim 7, wherein said copper foil and saidisolative layer has a blind hole at said rerouted location covered withsaid thin metallic layer.
 9. The metallic bump structure according toclaim 7, wherein said copper foil and said isolative layer has a blindhole at said rerouted location filled with a conductive paste.
 10. Themetallic bump structure according to claim 7, further comprising: asecond metallic material on a top surface of said metallic material atsaid rerouted location for an appropriate thickness.
 11. The metallicbump structure according to claim 10, wherein said second metallicmaterial is one of gold, copper, tin, nickel, solder, and a combinationthereof.
 12. The metallic bump structure according to claim 7, furthercomprising: a second isolative layer and a second copper foil in thisorder on said active side of said semiconductor die, said secondisolative layer and said second copper foil having a second via at saidintermediate location; a second thin metallic layer at least in saidsecond via; a second metallic material above said second copper foil andsaid second isolative layer laterally extends from said second via tosaid rerouted location of said metallic bump; and a third metallicmaterial on a top surface of said second metallic material at saidrerouted location for an appropriate thickness.
 13. The metallic bumpstructure according to claim 12, wherein said second isolative layer andsaid second copper foil have a blind hole at said rerouted locationcovered with said second thin metallic layer and filled with said secondmetallic material.
 14. The metallic bump structure according to claim12, wherein said second isolative layer and said second copper foil havea blind hole at said rerouted location filled with a conductive paste.15. The metallic bump structure according to claim 12, wherein saidsecond and third metallic materials are one of gold, copper, tin,nickel, solder, and a combination thereof.
 16. A metallic bump structureon an I/O pad on an active side of a semiconductor die, comprising: anisolative layer on said active side of said semiconductor die, saidisolative layer having a via above said I/O pad; a thin metallic layeron a top surface of said isolative layer and in said via connecting saidI/O pad; and a metallic material filled in said via and extendedvertically above said thin metallic layer and said isolative layer foran appropriate thickness.
 17. The metallic bump structure according toclaim 16, further comprising: if said I/O pad is made of aluminum orsaid I/O pad has an anti-oxidation layer made of aluminum, a zinc layeron a top surface of said aluminum I/O pad or said aluminumanti-oxidation layer.
 18. The metallic bump structure according to claim16, wherein said isolative layer is in one of a temporarily cured stateand a liquid state before being applied to said active side.
 19. Themetallic bump structure according to claim 16, wherein said thinmetallic layer is made of one of copper and nickel.
 20. The metallicbump structure according to claim 16, wherein said metallic material isone of gold, copper, tin, nickel, solder, and a combination thereof. 21.The metallic bump structure according to claim 16, further comprising: acoating layer for anti-oxidation at least on a top surface of saidmetallic material.
 22. The metallic bump structure according to claim16, wherein said metallic material laterally extends above said thinmetallic layer and said isolative layer from said via to one of arerouted location and an intermediate location of a metallic bump. 23.The metallic bump structure according to claim 22, wherein saidisolative layer has a blind hole at said rerouted location covered withsaid thin metallic layer.
 24. The metallic bump structure according toclaim 22, wherein said isolative layer has a blind hole at said reroutedlocation filled with a conductive paste.
 25. The metallic bump structureaccording to claim 22, further comprising: a second metallic material ona top surface of said metallic material at said rerouted location for anappropriate thickness.
 26. The metallic bump structure according toclaim 25, wherein said second metallic material is one of gold, copper,tin, nickel, solder, and a combination thereof.
 27. The metallic bumpstructure according to claim 22, further comprising: a second isolativelayer and a second copper foil in this order on said active side of saidsemiconductor die, said second isolative layer and said second copperfoil having a second via at said intermediate location; a second thinmetallic layer at least in said second via; a second metallic materialabove said second copper foil and said second isolative layer laterallyextends from said second via to said rerouted location of said metallicbump; and a third metallic material on a top surface of said secondmetallic material at said rerouted location for an appropriatethickness.
 28. The metallic bump structure according to claim 27,wherein said second isolative layer has a blind hole at said reroutedlocation covered with said second thin metallic layer and filled withsaid second metallic material.
 29. The metallic bump structure accordingto claim 27, wherein said second isolative layer has a blind hole atsaid rerouted location filled with a conductive paste.
 30. The metallicbump structure according to claim 27, wherein said second and thirdmetallic materials are one of gold, copper, tin, nickel, solder, and acombination thereof.